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www.lansdale.com page 1 of 19 issue 0 ml145026 ml145027 ml145028 encoder and decoder pairs legacy device: motorola/freescale mc145026, MC145027, mc145028 these devices are designed to be used as encoder/decoder pairs in remote control applications. the ml145026 encodes nine lines of information and serially sends this information upon receipt of a transmit enable (te) signal. the nine lines may be encoded with trinary data (low, high, or open) or binary data (low or high). the words are transmitted twice per encoding sequence to increase security. the ml145027 decoder receives the serial stream and interprets five of the trinary digits as an address code. thus, 243 addresses are possible. if binary data is used at the encoder, 32 addresses are possible. the remaining serial information is interpreted as four bits of binary data. the valid trans- mission (vt) output goes high on the ml145027 when two conditions are met. first, two addresses must be consecutively received (in one encoding sequence) which both match the local address. second, the 4 bits of data must match the last valid data received. the active vt indicates that the information at the data output pins has been updated. the ml145028 decoder treats all nine trinary digits as an address which allows 19,683 codes. if binary data is encoded, 512 codes are possible. the vt output goes high on the ml145028 when two addresses are consecu- tively received (in one encoding sequence) which both match the local address. ? operating temperature range: t a = ?40 to + 85? ? very?ow standby current for the encoder: 300 na maximum @ 25? ? interfaces with rf, ultrasonic, or infrared modulators and demodulators ? rc oscillator, no crystal required ? high external component tolerance; can use 5% components ? internal power?n reset forces all decoder outputs low ? operating voltage range: ml145026 = 2.5 to 18 v* ml145027, ml145028 = 4.5 to 18 v ? for infrared applications, see application note an1016/d pin assignments ml145026 encoder ml145028 decoders ml145027 decoders 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 c tc r tc te d o u t v dd a8/d8 a9/d9 r s a4 a3 a2 a1 v ss a7/d7 a6/d6 a5 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 d9 d8 d7 d6 v dd d in r 2 /c 2 vt a4 a3 a2 a1 v ss c 1 r 1 a5 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 a9 a8 a7 a6 v dd d in r 2 /c 2 vt a4 a3 a2 a1 v ss c 1 r 1 a5 p dip 16 = ep plastic dip case 648 so 16 = -5p sog package case 751b so 16w = -5p sog package case 751g 16 1 16 1 16 1 cross reference/ordering information motorola p dip 16 mc145026p ml145026ep so 16 mc145026d ml145026-5p p dip 16 MC145027p ml145027ep so 16 MC145027dw ml145027-5p p dip 16 mc145028p ml145028ep so 16 mc145028dw ml145028- 5p lansdale package note : lansdale lead free ( pb ) product, as it becomes available, will be identified by a part number prefix change from ml to mle . cmos
www.lansdale.com page 2 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 figure 1. ml145026 encoder block diagram te 15 ring counter and 1?of?9 decoder 9 8 76543 21 1 2 3 4 5 6 7 9 10 r s r tc c tc 13 12 14 3?pin oscillator and enable 4 divider data select and buffer d o u t trinary detector v dd = pin 16 v ss = pin 8 a1 a2 a3 a4 a5 a6/d6 a7/d7 a8/d8 a9/d9 11 543 21 sequencer circuit 1 2 3 4 5 a1 a2 a3 a4 a5 control logic 11 15 d6 h c t a l vt r e t s i g e r t f i h s t i b ? 4 9 d in data extractor v dd = pin 16 v ss = pin 8 c 1 c 2 r 2 r 1 76 figure 2. ml145027 decoder block diagram 10 d7 d8 d9 14 13 12
www.lansdale.com page 3 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 98 76543 21 sequencer circuit 1 2 3 4 5 15 14 13 12 a1 a2 a3 a4 a5 a6 a7 a8 a9 control logic 9?bit shift register 9 d in 11 vt data extractor figure 3. ml145028 decoder block diagram v dd = pin 16 v ss = pin 8 c 1 c 2 r 2 r 1 76 10 maximum ratings* (volt a ge s referenced to v ss ) rating symbol value unit v dd dc s u pply volt a ge ? 0.5 to + 18 v v dd dc s u pply volt a ge ? 0.5 to + 10 v v in dc inp u t volt a ge ? 0.5 to v dd + 0.5 v v o u t dc o u tp u t volt a ge ? 0.5 to v dd + 0.5 v i in dc inp u t c u rrent, per pin 10 ma i o u t dc o u tp u t c u rrent, per pin 10 ma p d power di ss ip a tion, per p a ck a ge 500 mw t s tg stor a ge temper a t u re ? 65 to + 150 c t l le a d temper a t u re, 1 mm from c as e for 10 second s 260 c *m a xim u m r a ting s a re tho s e v a l u e s beyond which d a m a ge to the device m a y occ u r. f u nc- tion a l oper a tion s ho u ld be re s tricted to the limit s in the electric a l ch a r a cteri s tic s t a ble s or pin de s cription s s ection. thi s device cont a in s protection circ u itry to g ua rd a g a in s t d a m a ge d u e to high s t a tic volt a ge s or electric field s . however, prec au - tion s m us t be t a ken to a void a pplic a tion s of a ny volt a ge higher th a n m a xim u m r a ted volt a ge s to thi s high?imped a nce circ u it. for proper oper a tion, v in a nd v o u t s ho u ld be con s tr a ined to the r a nge v ss (v in or v o u t ) v dd .
www.lansdale.com page 4 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 electrical characteristics ? ml145026 * , ml145027, and ml145028 (volt a ge referenced to v ss ) guaranteed limit v dd ? 40 c 25 c 85 c symbol characteristic v dd v min max min max min max unit v ol low?level o u tp u t volt a ge (v in = v dd or 0) 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 v v oh high?level o u tp u t volt a ge (v in = 0 or v dd ) 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 ? ? ? v v il low?level inp u t volt a ge (v o u t = 4.5 or 0.5 v) (v o u t = 9.0 or 1.0 v) (v o u t = 13.5 or 1.5 v) 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 v v ih high?level inp u t volt a ge (v o u t = 0.5 or 4.5 v) (v o u t = 1.0 or 9.0 v) (v o u t = 1.5 or 13.5 v) 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 ? ? ? 3.5 7.0 11 ? ? ? v i oh high?level o u tp u t c u rrent (v o u t = 2.5 v) (v o u t = 4.6 v) (v o u t = 9.5 v) (v o u t = 13.5 v) 5.0 5.0 10 15 ? 2.5 ? 0.52 ? 1.3 ? 3.6 ? ? ? ? ? 2.1 ? 0.44 ? 1.1 ? 3.0 ? ? ? ? ? 1.7 ? 0.36 ? 0.9 ? 2.4 ? ? ? ? ma i ol low?level o u tp u t c u rrent (v o u t = 0.4 v) (v o u t = 0.5 v) (v o u t = 1.5 v) 5.0 10 15 0.52 1.3 3.6 ? ? ? 0.44 1.1 3.0 ? ? ? 0.36 0.9 2.4 ? ? ? ma i in inp u t c u rrent ? te (ml145026, p u ll?up device) 5.0 10 15 ? ? ? ? ? ? 3.0 16 35 11 60 120 ? ? ? ? ? ? a i in inp u t c u rrent r s (ml145026), d in (ml145027, ml145028) 15 ? 0.3 ? 0.3 ? 1.0 a i in inp u t c u rrent a1 ? a5, a6/d6 ? a9/d9 (ml145026), a1 ? a5 (ml145027), a1 ? a9 (ml145028) 5.0 10 15 ? ? ? ? ? ? ? ? ? 110 500 1000 ? ? ? ? ? ? a c in inp u t c a p a cit a nce (v in = 0) ? ? ? ? 7.5 ? ? pf i dd q u ie s cent c u rrent ? ml145026 5.0 10 15 ? ? ? ? ? ? ? ? ? 0.1 0.2 0.3 ? ? ? ? ? ? a i dd q u ie s cent c u rrent ? ml145027, ml145028 5.0 10 15 ? ? ? ? ? ? ? ? ? 50 100 150 ? ? ? ? ? ? a i dd dyn a mic s u pply c u rrent ? ml145026 (f c = 20 khz) 5.0 10 15 ? ? ? ? ? ? ? ? ? 200 400 600 ? ? ? ? ? ? a i dd dyn a mic s u pply c u rrent ? ml145027, ml145028 (f c = 20 khz) 5.0 10 15 ? ? ? ? ? ? ? ? ? 400 800 1200 ? ? ? ? ? ? a *al s o s ee next electric a l ch a r a cteri s tic s t a ble for 2.5 v s pecific a tion s .
www.lansdale.com page 5 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 electrical characteristics ? ml145026 (volt a ge referenced to v ss ) guaranteed limit v dd ? 40 c 25 c 85 c symbol characteristic v dd v min max min max min max unit v ol low?level o u tp u t volt a ge (v in = 0 v or v dd ) 2.5 ? 0.05 ? 0.05 ? 0.05 v v oh high?level o u tp u t volt a ge (v in = 0 v or v dd ) 2.5 2.45 ? 2.45 ? 2.45 ? v v il low?level inp u t volt a ge (v o u t = 0.5 v or 2.0 v) 2.5 ? 0.3 ? 0.3 ? 0.3 v v ih high?level inp u t volt a ge (v o u t = 0.5 v or 2.0 v) 2.5 2.2 ? 2.2 ? 2.2 ? v i oh high?level o u tp u t c u rrent (v o u t = 1.25 v) 2.5 0.28 ? 0.25 ? 0.2 ? ma i ol low?level o u tp u t c u rrent (v o u t = 0.4 v) 2.5 0.22 ? 0.2 ? 0.16 ? ma i in inp u t c u rrent (te ? p u ll?up device) 2.5 ? ? 0.09 1.8 ? ? a i in inp u t c u rrent (a1?a5, a6/d6?a9/d9) 2.5 ? ? ? 25 ? ? a i dd q u ie s cent c u rrent 2.5 ? ? ? 0.05 ? ? a i dd dyn a mic s u pply c u rrent (f c = 20 khz) 2.5 ? ? ? 40 ? ? a switching characteristics ? ml145026*, ml145027, and ml145028 (c l = 50 pf, t a = 25 c) figure guaranteed limit symbol characteristic figure no. v dd min max unit t tlh , t thl o u tp u t tr a n s ition time 4,8 5.0 10 15 ? ? ? 200 100 80 n s t r d in ri s e time ? decoder s 5 5.0 10 15 ? ? ? 15 15 15 s t f d in f a ll time ? decoder s 5 5.0 10 15 ? ? ? 15 5.0 4.0 s f o s c encoder clock freq u ency 6 5.0 10 15 0.001 0.001 0.001 2.0 5.0 10 mhz f decoder freq u ency ? referenced to encoder clock 12 5.0 10 15 1.0 1.0 1.0 240 410 450 khz t w te p u l s e width ? encoder s 7 5.0 10 15 65 30 20 ? ? ? n s *al s o s ee next switching ch a r a cteri s tic s t a ble for 2.5 v s pecific a tion s . switching characteristics ? ml145026 (c l = 50 pf, t a = 25 c) figure guaranteed limit symbol characteristic figure no. v dd min max unit t tlh , t thl o u tp u t tr a n s ition time 4, 8 2.5 ? 450 n s f o s c encoder clock freq u ency 6 2.5 1.0 250 khz t w te p u l s e width 7 2.5 1.5 ? s
www.lansdale.com page 6 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 10% 90% any output t tlh t thl figure 4. figure 5. figure 6. figure 7. figure 8. test circuit 10% 90% d in t f t r v dd v ss r tc 50% 1/f o s c te 50% v dd v ss t w device under test * incl u de s a ll probe a nd fixt u re c a p a cit a nce. c l * output test point
www.lansdale.com page 7 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 o pe rating charact e ristics ml145026 the encoder serially transmits trinary data as defined by the state of the a1 ?a5 and a6/d6 ?a9/d9 input pins. these pins may be in either of three states (low, high, or open) allow- ing 19,683 possible codes. the transmit sequence is initiated by a low level on the te input pin. upon power?p, the ml145026 can continuously transmit as long as te remains low (also, the device can transmit two?ord sequences by pulsing te low). however, no ml145026 application should be designed to rely upon the first data word transmitted imme- diately after power?p because this word may be invalid. between the two data words, no signal is sent for three data periods (see figure 10). each transmitted trinary digit is encoded into pulses (see figure 11). a logic 0 (low) is encoded as two consecutive short pulses, a logic 1 (high) as two consecutive long pulses, and an open (high impedance) as a long pulse followed by a short pulse. the input state is determined by using a weak?utput device to try to force each input high then low. if only a high state results from the two tests, the input is assumed to be hard wired to v dd . if only a low state is obtained, the input is assumed to be hardwired to v ss . if both a high and alow can be forced at an input, an open is assumed and is encoded as such. the ?igh?and ?ow?levels are 70% and 30% of the supply voltage as shown in the electrical characteristics table. the weak ?utput?device sinks/sources up to110 ? at a 5 v supply level, 500 ? at 10 v, and 1 ma at 15 v. the te input has an internal pull?p device so that a simple switch may be used to force the input low. while te is high and the second?ord transmission has timed out, the encoder is completely disabled, the oscillator is inhibited, and the cur- rent drain is reduced to quiescent current. when te is brought low, the oscillator is started and the transmit sequence begins. the inputs are then sequentially selected, and determinations are made as to the input logic states. this information is serial- ly transmitted via the d out pin. ml145027 this decoder receives the serial data from the encoder and outputs the data, if it is valid. the transmitted data, consisting of two identical words, is examined bit by bit during reception. the first five trinary digits are assumed to be the address. if the received address matches the local address, the next four (data) bits are internally stored, but are not transferred to the output data latch. as the second encoded word is received, the address must again match. if a match occurs, the new data bits are checked against the previously stored data bits. if the two nibbles of data (four bits each) match, the data is transferred to the output data latch by vt and remains until new data replaces it. at the same time, the vt output pin is brought high and remains high until an error is received or until no input signal is received for four data periods (see figure 10). although the address information may be encoded in tri- nary, the data information must be either a 1 or 0. a trinary (open) data line is decoded as a logic 1. ml145028 this decoder operates in the same manner as the ml145027 except that nine address lines are used and no data output is available. the vt output is used to indicate that a valid address has been received. for transmission security, two identical transmitted words must be consecutively received before a vt output signal is issued. the ml145028 allows 19,683 addresses when trinary levels are used. 512 addresses are possible when binary levels are used. p in d e scri p tions ml145026 e ncod e r a1 ?a5, a6/d6 ?a9/d9 address, address/data inputs ( p ins 1 ?7, 9, and 10) these address/data inputs are encoded and the data is sent serially from the encoder via the d out pin. rs, ctc, rtc ( p ins 11, 12, and 13) these pins are part of the oscillator section of the encoder (see figure 9). if an external signal source is used instead of the internal oscillator, it should be connected to the rs input and the rtc and ctc pins should be left open. t e transmit e nable ( p in 14) this active?ow transmit enable input initiates transmission when forced low. an internal pull?p device keeps this input normally high. the pull?p current is specified in the electrical characteristics table. d out data out ( p in 15) this is the output of the encoder that serially presents the encoded data word. v ss negative p ower supply ( p in 8) the most?egative supply potential. this pin is usually ground. v dd p ositive p ower supply ( p in 16). the most?ositive power supply pin. ml145027 and ml145028 d e cod e rs a1 ?a5, a1 ?a9 address inputs ( p ins 1 ?5)?l145027, address inputs ( p ins 1 ?5, 15, 14, 13, 12)?l145028 these are the local address inputs. the states of these pins must match the appropriate encoder inputs for the vt pin to go high. the local address may be encoded with trinary or binary data. d6 ?d9 data outputs ( p ins 15, 14, 13, 12)?l145027 only these outputs present the binary information that is on encoder inputs a6/d6 through a9/d9. only binary data is
www.lansdale.com page 8 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 acknowledged; a trinary open at the ml145026 encoder is decoded as a high level (logic 1). d in data in ( p in 9) this pin is the serial data input to the decoder. the input voltage must be at cmos logic levels. the signal source driv- ing this pin must be dc coupled. r 1 ,c 1 resistor 1, capacitor 1 ( p ins 6, 7) as shown in figures 2 and 3, these pins accept a resistor and capacitor that are used to determine whether a narrow pulse or wide pulse has been received. the time constant r 1 x c 1 should be set to 1.72 encoder clock periods: r 1 c 1 = 3.95 r tc c tc r 2 /c 2 resistor 2/capacitor 2 ( p in 10) as shown in figures 2 and 3, this pin accepts a resistor and capacitor that are used to detect both the end of a received word and the end of a transmission. the time constant r 2 x c 2 should be 33.5 encoder clock periods (four data periods per figure 11): r 2 c 2 = 77 r tc c tc . this time constant is used to determine whether the d in pin has remained low for four data periods (end of transmission). a separate on?hip com- parator looks at the voltage?quivalent two data periods (0.4 r 2 c 2 ) to detect the dead time between received words within a transmission. vt valid transmission output ( p in 11) this valid transmission output goes high after the second word of an encoding sequence when the following conditions are satisfied: 1. the received addresses of both words match the local de-coder address, and 2. the received data bits of both words match. vt remains high until either a mismatch is received or no input signal is received for four data periods. v ss negative p ower supply ( p in 8) the most?egative supply potential. this pin is usually ground. v dd p ositive p ower supply ( p in 16) the most?ositive power supply pin.
www.lansdale.com page 9 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 r s c tc r tc 11 12 13 internal enable figure 9. encoder oscillator information thi s o s cill a tor oper a te s a t a freq u ency determined by the extern a l rc network; i.e., f 1 2.3 r tc c tc (hz) for 1 khz f 400 khz where: c tc = c tc + c l a yo u t + 12 pf r s 2 r tc r s 20 k r tc 10 k 400 pf < c tc < 15 f the v a l u e for r s s ho u ld be cho s en to be 2 time s r tc . thi s r a nge en su re s th a t c u rrent thro u gh r s i s in s ignific a nt comp a red to c u rrent thro u gh r tc . the u pper limit for r s m us t en su re th a t r s x 5 pf (inp u t c a p a cit a nce) i s s m a ll com- p a red to r tc x c tc . for freq u encie s o u t s ide the indic a ted r a nge, the form u l a i s le ss a cc u r a te. the minim u m recommended o s cill a tion freq u ency of thi s circ u it i s 1 khz. s us - ceptibility to extern a lly ind u ced noi s e s ign a l s m a y occ u r for freq u encie s below 1 khz a nd/or when re s i s tor s u tilized a re gre a ter th a n 1 m ? . figure 10. timing diagram pw min te 2 word transmission encoder continuous transmission encoder oscillator (pin 12) d o u t (pin 15) vt (pin 11) data outputs 1.1 (r 2 c 2 ) decoder encoding sequence 1st digit high 2nd word 1st word open low 9th digit 9th digit 1st digit 2 4 6 6 1 8 1 0 2 2 2 4 2 6 2 8 2 0 3 0 8 2 8 4 8 6 8 8 8 0 9 4 1 1 6 1 1 8 1 1 0 2 1 2 2 1 8 7 1 0 8 1 2 8 1 4 8 1
www.lansdale.com page 10 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 data period encoder oscillator (pin 12) d o u t (pin 15) encoded ?one? encoded ?zero? encoded ?open? figure 11. encoder data waveforms 500 400 300 200 100 v dd = 15 v v dd = 10 v v dd = 5 v figure 12. f max vs c layout ? decoders only c l a yo u t (pf) on pins 1 ? 5 (ml145027); pins 1 ? 5 and 12 ? 15 (ml145028) ) z h k ( f ) k c o l c r e d o c n e o t . f e r ( x a m 10 20 30 40 50
www.lansdale.com page 11 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 no yes figure 13. ml145027 flowchart no has the transmission begun? does this data match the previously stored data? disable vt on the 1st address mismatch disable vt on the 1st data mismatch disable vt is this at least the 2nd consecutive match since vt disable? does the 5?bit address match the address pins? store the 4?bit data yes yes latch data onto output pins and activate vt have 4?bit times passed? has a new transmission begun? yes no no yes no yes no
www.lansdale.com page 12 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 has the transmission begun? no yes yes yes no no does the address match the address pins? disable vt on the 1st address mismatch and ignore the rest of this word disable vt is this at least the 2nd consecutive match since vt disable? activate vt have 4?bit times passed? has a new transmission begun? yes yes no no

www.lansdale.com page 1 3 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 ml145027 and ml145028 timing to verify the ml145027 or ml145028 timing, check the- waveforms on c 1 (pin 7) and r 2 /c 2 (pin 10) as compared to the incoming data waveform on d in (pin 9). the r? decay seen on c1 discharges down to 1/3 v dd before being reset to v dd . this point of reset (labelled ?os in figure 15) is the point in time where the decision is made whether the data seen on d in is a 1 or 0. dos should not be too close to the d in data edges or intermittent operation may occur. the other timing to be checked on the ml145027 and ml145028 is on r 2 /c 2 (see figure 16). the r? decay is continually reset to v dd as data is being transmitted. only between words and after the end?f?ransmission (eot) does r 2 /c 2 decay significantly from v dd . r 2 /c 2 can be used to identify the internal end?f?ord (eow) timing edge which is generated when r 2 /c 2 decays to 2/3 v dd . the internal eot timing edge occurs when r 2 /c 2 decays to 1/3 v dd . when the waveform is being observed, the r? decay should go down between the 2/3 and 1/3 v dd levels, but not too close to either level before data transmission on d in resumes. verification of the timing described above should ensure a good match between the ml145026 transmitter and the ml145027 and ml145028 receivers. v dd 0 v d in v dd 2/3 1/3 0 v c1 dos dos
v dd 2/3 1/3 0 v r2/c2 eot

eow
www.lansdale.com page 14 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 v dd te 5 trinary addresses 4?bit binary data a1 a2 a3 a4 a5 d6 d7 d8 d9 1 2 3 4 5 6 7 9 10 14 16 15 d o u t 0.1 f ml145026 8 12 11 r tc r s v dd 13 c tc repeat of above ml145027 v dd 0.1 f 16 d in 9 6 7 10 r2 c 2 r1 c 1 1 2 3 4 5 15 14 13 12 11 d6 d7 d8 d9 vt v dd 5 trinary addresses a1 a2 a3 a4 a5 figure 17. typical application c tc = c tc + c l a yo u t + 12 pf 100 pf c tc 15 f r tc 10 k ? ; r s 2 r tc r 1 10 k ? c 1 400 pf r 2 100 k ? c 2 700 pf f o s c = 1 2.3 r tc c tc r 1 c 1 = 3.95 r tc c tc r 2 c 2 = 77 r tc c tc example r/c values (all resistors and capacitors are 5%) (c tc = c tc + 20 pf) f osc (khz) r tc c tc r s r 1 c 1 r 2 c 2 362 181 88.7 42.6 21.5 8.53 1.71 10 k 10 k 10 k 10 k 10 k 10 k 50 k 20 k 20 k 20 k 20 k 20 k 20 k 100 k 120 pf 240 pf 490 pf 1020 pf 2020 pf 5100 pf 5100 pf 10 k 10 k 10 k 10 k 10 k 10 k 50 k 100 k 100 k 100 k 100 k 100 k 200 k 200 k 8 910 pf 1800 pf 3900 pf 7500 pf 0.015 f 0.02 f 0.1 f 470 pf 910 pf 2000 pf 3900 pf 8200 pf 0.02 f 0.02 f repeat of above
www.lansdale.com page 15 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 infrar e d transmitt e r in figure 18, the ml145026 encoder is set to run at an os- cillator frequency of about 4 to 9 khz. thus, the time required for a complete two?ord encoding sequence is about 20 to 40 ms. the data output from the encoder gates an rc oscillator running at 50 khz; the oscillator shown starts rapidly enough to be used in this application. when the ?end?button is not depressed, both the ml145026 and oscillator are in a low?ower standby state. the rc oscillator has to be trimmed for 50 khz and has some drawbacks for frequency stability. a superior system uses a ceramic resonator oscillator running at 400 khz. this oscillator feeds a divider as shown in figure 19. the unused inputs of the mc14011ub must be grounded. the mled81 ired is driven with the 50 khz square wave at about 200 to 300 ma to generate the carrier. if desired, two ireds wired in series can be used (see application note an1016 for more information). the bipolar ired switch, shown in figure 18, offers two advantages over a fet. first, a logic fet has too much gate capacitance for the mc14011ub to drive without waveform distortion. second, the bipolar drive permits lower supply voltages, which are an advantage in portable battery?owered applications. the configuration shown in figure 18 operates over a supply range of 4.5 to 18 v. a low?oltage system which operates down to 2.5 v could be realized if the oscillator section of a mc74hc4060 is used in place of the mc14011ub. the data output of the ml145026 is inverted and fed to the reset pin of the mc74hc4060. alternately, the mc74hcu04 could be used for the oscillator. for information on the mc14011ub, mc74hcu04 and mc74hc4060 consult on semiconductor. infrar e d r e c e iv e r the receiver in figure 20 couples an ir?ensitive diode to input preamp a1, followed by band?ass amplifier a2 with again of about 10. limiting stage a3 follows, with an output of about 800 mv p?. the limited 50 khz burst is detected by comparator a4 that passes only positive pulses, and peak?etect- ed and filtered by a diode/rc network to extract the data enve- lope from the burst. comparator a5 boosts the signal to logic levels compatible with the ml145027/28 data input. the d in pin of these decoders is a standard cmos high?mpedance input which must not be allowed to float. therefore, direct cou- pling from a5 to the decoder input is utilized. shielding should be used on at least a1 and a2, with good ground and high?ensitivity circuit layout techniques applied. for operation with supplies higher than + 5 v, limiter a4s pos- itive output swing needs to be limited to 3 to 5 v. this is accomplished via adding a zener diode in the negative feed- back path, thus avoiding excessive system noise. the biasing resistor stack should be adjusted such that v3 is 1.25 to1.5 v. this system works up to a range of about 10 meters. the gains of the system may be adjusted to suit the individual design needs. the 100 ? resistor in the emitter of the first 2n5088 and the 1 k ? resistor feeding a2 may be altered if dif- ferent gain is required. in general, more gain does not nec- essarily result in increased range. this is due to noise floor limitations. the designer should increase transmitter power and/or increase receiver aperature with fresnal lensing to greatly improve range. see application note an1016 for addi- tional information. for information on the mc34074 contact on semiconductor. trinary switch manufactur e rs midland ross?lectronic connector div. greyhill augat/alcoswitch aries electronics the above companies may not have the switches in a dip. for more information, call them or consult eem electronic engineers master catalog or the gold book. ask for s p dt with center off. alternative: an spst can be placed in series between a spdt and the encoder or decoder to achieve trinary action. lansdale cannot recommend one supplier over another and in no way suggests that this is a complete listing of trinary switch manufacturers. legacy applications information
www.lansdale.com page 16 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 10 k ? 220 k ? send te 9 r s c tc r tc ml145026 switches 100 k ? for approx. 4 khz 47 k ? for approx. 9 khz 1000 pf d o u t mc14011ub mc14011ub 220 k ? 0.01 f select for 200 ma to 300 ma mled81 use of 2 mled81 s is optional mpsa13 or mpsw13 adjust/select for f = 50 khz (approx. 100 k ? ) figure 18. ir e d transmitter using r c oscillator to generate carrier frequency v+ 50 khz to driver transistor x1 = 400 khz ceramic resonator panasonic efd?a400k04b or equivalent mc14024 clk x1 470 pf mc14011ub d o u t from ml145026 1m ? 470 pf q3 figure 19. using a ceramic r esonator to generate carrier frequency reset v+ mc14011ub
www.lansdale.com page 17 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 figure 20. infrared r eceiver 10 f 22 k ? optical filter 10 k ? 10 k ? 10 k ? 100 ? 6.8 k ? 2.2 k ? 1 f 1n914 1n914 100 k ? + ? + ? + ? + ? +5 v 0.01 f 1 k ? 1 mh ? toko type 7pa or 10pa or equivalent 0.01 f 4.7 k ? a2 a3 a4 a5 10 k ? v1 v1 v2 1 m ? 1n914 1 k ? 1000 pf 47 k ? 22 k ? 1 m ? v3 1000 pf 390 k ? for approx. 4 khz 180 k ? for approx. 9 khz 750 k ? for approx. 4 khz 360 k ? for approx. 9 khz 0.01 f c1 r1 r2/c2 vt v ss v dd 4 9 for ml145027 5 for ml145028 address switches data out ml145027 only +5 v 10 f 10 f 4.7 k ? 2.2 k ? 390 ? 2.7 k ? 10 f v2 2.7 v d in 0.01 f 1/4 mc34074 +5 v 2n5088 2n5086 2n5088 1/4 mc34074 1/4 mc34074 1/4 mc34074 a1 v3 1.3 v v1 2.5 v ml145027/28 10 f
www.lansdale.com page 1 8 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 outline dimensions p dip 16 = ep (ml145026ep, ml145027ep, ml145028ep) plastic dip (dual in?line package) case 648?08 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inc he s a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 so 16 = -5p sog (small outline gull?wing) package (ml145026-5p) case 751b?05 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b ? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inc he s millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
www.lansdale.com page 19 of 19 issue 0 lan s dale s emiconductor, inc. ml145026, ml145027, ml14502 8 so 16w = -5p outline dimensions sog (small outline gull?wing) package (ml145027-5p, ml145028-5p) cas e 751g?02 dim min max min max inc he s millimeters a 10.15 10.45 0.400 0.411 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 m b m 0.010 (0.25) notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. ?a? ?b ? p 8x g 14x d 16x seating plane ?t? s a m 0.010 (0.25) b s t 16 9 8 1 f j r x 45 m c k lansdale s emiconductor reserves the right to make changes without further notice to any products herein to improve relia b ili- ty, function or design. lansdale does not assume any lia b ility arising out of the application or use of any product or circuit descri b ed herein; neither does it convey any license under its patent rights nor the rights of others. typical parameters which may b e provided in lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. all operating parameters, including typicals must b e validated for each customer application b y the customer?s technical experts. lansdale s emiconductor is a registered trademark of lansdale s emiconductor, inc.

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